The above-identified related patents and patent applications disclose a method of fabricating multichip integrated circuits employing polymer dielectric overlayers having via holes therein and patterned metallization layers thereon for interconnection of contact pads of the various integrated circuits within themselves, to each other and to external circuits. Briefly, the process comprises laminating a first polymer dielectric layer which may preferably be a polyimide over the integrated circuit chips which are disposed on a substrate. Thereafter, via holes are preferably formed in the dielectric layer in alignment with contact areas on the various integrated circuit chips which are to be connected via the patterned metallization. This via hole formation is preferably done using laser drilling by one of the processes described in the related U.S. Pat. Nos. 4,617,085, 4,714,516 and 4,764,485 or patent application Ser. No. 310,489, filed Feb. 14, 1989, all cited above, or by any other appropriate process. Thereafter, a metallization layer is formed over the polymer dielectric and patterned to provide the desired metallization pattern. In order to form a multilayer metallization pattern, a second polymer dielectric layer is then formed over the first polymer layer and the first metallization layer. This second dielectric layer may preferably comprise a siloxane polyimide copolymer. Following the formation of this siloxane polyimide layer, via holes are laser drilled to provide openings for electrical connection to the first metallization layer. The structure is then plasma etched to ensure that all debris is removed from the via holes prior to deposition of the second metal layer. After patterning of the second metal layer, a second layer of siloxane polyimide dielectric may be formed over the first layer of siloxane polyimide dielectric and the metallization pattern thereon to provide additional interconnection structures. We have found that when this is done, the second siloxane polyimide copolymer layer has a crazed or cracked appearance and has an exposed surface which is rippled or rough. This surface is sufficiently rough that formation of a patterned layer of metal thereon becomes difficult. These characteristics raise substantial reliability concerns with respect to electronic systems in which interconnections are made in this manner.
A method is needed for reliably forming high quality, multilayer siloxane polyimide dielectric structures having patterned metallization layers within the siloxane polyimide structure.